The present invention relates generally to integrated circuits such as system-on-chip (SOC) devices, and, more particularly, to a circuit and method for preventing multiple resets from occurring in such devices.
Power management units in a “System on Chip” (SOC) use Power-on Reset (POR) and Low Voltage Detector (LVD) techniques to initialize the SOC to a known state. When an SOC boots, many of its constituent parts, and particularly those comprising the power management circuits, work with default threshold values for LVD, POR and on-chip voltage regulator output voltages. During the boot procedure, trim values are loaded and default values of LVD POR, band gap reference (BGR) circuits and voltage regulators are changed. If the trimmed and untrimmed values of a given circuit are different, there is a possibility that the SOC will enter a loop of multiple resets for a short duration or even indefinitely. This behavior is undesirable, particularly if the SOC is used in safety-critical systems such as medical or automotive systems.
For example if an LVD has an untrimmed threshold of 1.15 v and a trimmed threshold of 1.18 v, then during boot, when the core voltage reaches 1.15 v, a LVD ‘OK’ is released and the trim values are loaded. However, as soon as the trim values are loaded, the LVD thresholds will change to 1.18 v, which will cause a reset of the SOC if the core voltage, which is still rising, has not yet reached 1.18 v. Once a reset is generated, the trim values will be deleted and the LVD will revert to the 1.15 v threshold value and assert an ‘OK’ status. Consequently, the SOC will again start loading trim values, leading again to a change of the LVD threshold from 1.15 v to 1.18 v and another reset cycle may follow. Depending on SOC implementation, this cyclical resetting behaviour can cause the on-chip voltage regulators also to be reset and hence an infinite cycle of reset can follow. Multiple resets increase boot time and may even cause hardware deadlock from which the system may not recover. For battery operated systems, if the SOC does not exit this loop, it will lead to the battery being drained.
Another problem can arise during booting owing to large variation of IR drop on bond wires and die power grid resistance, for example, which can result in a sudden dip in voltage, which is seen by the various on-board voltage monitoring circuits. This sudden dip can trigger one or more low voltage detectors resulting in the SOC being put into reset. Once in reset, the current suddenly drops, supply voltage is restored to a higher value and consequently the SOC exits reset and then goes back into reset again.
Therefore, it would be advantageous to prevent multiple reset events in integrated circuits.